In the field of communications, wireless (RF) communication devices such as cellular telephones and other related physical transceiver structures continue to shrink in size while adding more and more features. In conjunction with this, the required board space or “footprint” of integrated circuit (IC) elements becomes a more critical design factor. Within such RF communication devices, a local oscillator (LO) signal is required for receiving and transmitting. A conventional VCO is typically used in a PLL to generate the LO signal. In the conventional arrangement, the VCO is typically provided as a separate discrete module. Similarly, filter components (e.g., capacitors . . . etc.) have conventionally been separate due to manufacturing constraints such as size. However, this results in increased costs and required circuit board area to accommodate the VCO module and separate filter components. As such, a desirable goal has been to integrate the VCO circuitry and filter components into a single integrated circuit (IC) package with other RF circuitry so as to reduce the cost and the required circuit board area.
Within mobile phone designs, IC elements have been developed that combine PLL and VCO functions on the same semiconductor chip. By integrating the PLL and VCO functions into a single chip, the board space required is reduced over designs that use discrete PLL and VCO circuits. This opens up critically needed board space for other functions in the latest mobile handsets, allowing them to include advanced differentiating features such as an integrated camera, MP3 player, Bluetooth, or other additional features.
FIG. 1 shows a simplified block diagram of a closed-loop frequency-control system based on the phase difference between an input clock signal and a feedback clock signal of a controlled oscillator where such a system is a conventional PLL 100. The major components in such a conventional PLL 100 include a phase frequency detector (PFD), charge pump, charging capacitor 102, loop filter, VCO 101, and divider. The PFD detects the difference in phase and frequency between the reference clock fref and feedback clock fx inputs and generates an “up” or “down” control signal based on whether the feedback frequency is lagging or leading the reference frequency. These “up” or “down” control signals determine whether the VCO 101 needs to operate at a higher or lower frequency, respectively. The PFD outputs these “up” and “down” signals to a charge pump. If the charge pump receives an up signal, current is driven into the loop filter. Conversely, if it receives a down signal, current is drawn from the loop filter. The loop filter converts these signals to a control voltage that is used to bias the VCO 101.
Based on the control voltage, the VCO 101 in FIG. 1 oscillates at a higher or lower frequency, which affects the phase and frequency of the feedback clock. If the PFD produces an up signal, then the VCO 101 frequency increases. A down signal decreases the VCO 101 frequency. The VCO 101 stabilizes once the reference clock fref and feedback clock fx have the same phase and frequency. The loop filter filters out jitter by removing glitches from the charge pump and preventing voltage over-shoot. When the reference clock fref and the feedback clock fx are aligned, the PLL is considered locked. A divider is inserted to increase the VCO 101 frequency above the input reference frequency fref. While Type II PLL 100 functions suitably for most applications, the loop filter components are typically large and include capacitances that must be formed off chip due to their size. This results in added expense and unsuitability for contemporary RF devices with increasingly significant size constraints.
To reduce the size of loop filter components as used in FIG. 1, other known PLL devices have been formed with dual paths. FIG. 2 shows a simplified block diagram of dual path PLL 200 with similar major components as shown in PLL 100 of FIG. 1 including a PFD, VCO 201, and divider. Operation of such is identical to that described in relation to FIG. 1. However, two charge pumps exist with respective charging capacitors 202, 203. Capacitor 203 includes a resistance 204 in parallel. While passive capacitances are shown in the form of simple capacitors 202, 203, often these are formed by active circuitry including transistors. An adder is inserted prior to the VCO 201 and within the charging paths in order to combine the outputs of the charge pumps. Because of the two paths, the charging capacitors 202, 203 can be reduced in size such that they may be small enough to place them on-chip and still provide the effective large capacitance necessary for PLL operation. Disadvantageously, the required circuitry forming the adder function introduces a significant amount of noise to the PLL 200.
What is needed therefore is a PLL that may be substantially integrated on a single chip without reliance on external circuit elements while minimizing noise.